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Memory

This unit delves into the fundamental aspects of computer memory within the context of Computer Architecture and Organization. Memory, a vital component, significantly influences the efficiency and functioning of computers. The topics covered include the Classification of Memories, exploring RAM organization, Static RAM, and Dynamic RAM. Additionally, we will examine ROM organization, including PROM, EPROM, EEPROM, and EAPROM. The concept of Memory Hierarchy will be discussed, shedding light on Cache Memory, Mapping techniques, and the importance of the locality of references. Advanced topics such as Virtual Memory will also be explored, focusing on demand paging, Page Faults, and Page Replacement strategies.

Memory Hierarchy

Memory is a fundamental component of digital computers, serving as the repository for data and programs. However, relying on a single type of memory poses limitations on the storage capacity and access speed. To address this, computer systems employ a concept known as Memory Hierarchy, which encompasses various memory levels to optimize performance.

RAM Organization

RAM Block Diagram

The block diagram below illustrates the key components of a Random Access Memory (RAM).

RAM Block Diagram
  • The RAM has a capacity of 128 words, with each word consisting of eight bits. This configuration necessitates a 7-bit address for memory addressing. The 8-bit bidirectional data bus facilitates the transfer of data to and from the memory.
  • The memory's read and write operations are controlled by specific lines. The read line is utilized for fetching data from the RAM, while the write line is responsible for storing data into the memory.
  • Two control lines, CS1 and CS2, are employed to activate the RAM chip. It's important to note that the RAM becomes active when CS1 equals 1 and CS2 equals 0. These control lines play a crucial role in managing the access and functionality of the memory.
  • In summary, the RAM block diagram demonstrates the interplay of various components, including the address lines, data bus, read and write control lines, and chip select lines, to enable efficient memory operations.

The function table

  • Case 1 : When CS1 = 0 and CS2 = 0. In this condition RAM is not activated. So reading and writing is not possible.
  • Case 2 : When CS1 = 0 and CS2 = 1. In this condition RAM is not activated. So reading and writing is not possible.
  • Case 3 : When CS1 = 1 and CS2 = 0. In this condition RAM is activated. But RD = 0 and WR = 0, so reading and writing is not possible.
  • Case 4 : When CS1 = 1 and CS2 = 0. In this condition RAM is activated. Now RD = 0 and WR = 1, so we can write (store) data into RAM.
  • Case 5 : When CS1 = 1 and CS2 = 0. In this condition RAM is activated. Now RD = 1 and WR = 0, so we can read (fetch) data from RAM.
  • Case 6 : When CS1 = 1 and CS2 = 1. In this condition RAM is not activated. So reading and writing is not possible.

Read-Only Memory (ROM)

Block Diagram of ROM

  • The block diagram illustrates the organization of a ROM chip, similar to RAM, but with the distinctive feature that ROM is designed for read-only operations, eliminating the need for a write line (WR).
  • In the presented diagram, a 512-byte ROM is showcased, characterized by nine address lines. These address lines collectively specify any one of the 512 locations within the ROM chip.
  • Activation of the ROM occurs when the chip select inputs CS1 = 1 and CS2 = 0. These control lines play a vital role in enabling access to the ROM, allowing the retrieval of stored data from specific memory locations.

Types of ROM

  • PROM (Programmable Read-Only Memory):
    • PROM is a type of read-only memory that allows users to program it once with desired data.
    • Users purchase a blank PROM and input the required data. Once programmed, the data becomes permanent and cannot be modified.
    • Programming PROM involves burning small fuses within the chip, making it a one-time programmable and non-erasable memory.
    • PROM is suitable for applications where the data is fixed and does not need frequent updates.
  • EPROM (Erasable and Programmable Read-Only Memory):
    • EPROM can be erased and reprogrammed using special electrical signals or ultraviolet (UV) rays.
    • EPROMs that employ UV rays for erasure are referred to as UVEPROM, while those using electrical signals are known as EEPROM (Electrically Erasable Programmable Read-Only Memory).
    • During programming, an electrical charge is stored in EPROM, and this charge is retained for more than 10 years, providing non-volatile memory storage.
    • EPROM offers the advantage of reusability, making it suitable for applications where data updates are required, but not as frequently as EEPROM.
  • EEPROM (Electrically Erasable Programmable Read-Only Memory):
    • EEPROM is programmed and erased electrically, allowing for greater flexibility compared to EPROM.
    • It supports erasing and reprogramming cycles, typically up to ten thousand times, making it more versatile for applications requiring frequent updates.
    • Both erasing and programming in EEPROM are relatively quick, taking about 4 to 10 milliseconds (ms).
    • EEPROM provides the capability to selectively erase and program specific memory locations, offering a granular approach to data modification.
    • Applications for EEPROM include settings storage in electronic devices, where frequent updates or customization of data are necessary.

Cache Memory

Types of Cache Memory

  • Level 1 Cache (L1 Cache):
    • L1 Cache is the primary cache located on the processor chip itself.
    • It is designed to store a small amount of frequently accessed data and instructions for quick retrieval.
    • Due to its proximity to the processor, L1 Cache offers extremely fast access times, contributing to enhanced overall system performance.
    • L1 Cache is further divided into separate caches for instructions (L1i) and data (L1d).
  • Level 2 Cache (L2 Cache):
    • L2 Cache is located on a separate chip but is still situated near the processor.
    • It has a larger capacity compared to L1 Cache and serves as a secondary cache layer.
    • L2 Cache helps bridge the speed gap between the processor and the main memory.
    • Both instructions and data are stored in the unified L2 Cache, making it a crucial component for optimizing system performance.
  • Level 3 Cache (L3 Cache):
    • L3 Cache is a shared cache that may be located on the processor chip or a separate chip.
    • It has an even larger capacity compared to L2 Cache and is shared among multiple processor cores within a system.
    • L3 Cache helps improve the overall efficiency of multi-core processors by providing a larger pool of shared cache memory.
    • Its larger size and shared nature make L3 Cache effective in handling diverse workloads and improving system-level performance.
  • Unified Cache:
    • Unified Cache combines the storage of instructions and data in a single cache, unlike separate L1i and L1d caches.
    • It simplifies cache management and reduces the complexity of addressing both instruction and data caches separately.
    • Unified Caches are commonly found in modern processors to streamline memory access and enhance overall efficiency.

Cache Mapping

Locality of References

Types of Localities:

  • Temporal Locality:
    • Temporal locality implies that current data being fetched may be needed again soon. To exploit this, the data or instruction is stored in the cache memory, eliminating the need to search the main memory for the same data repeatedly.
    • When the CPU fetches data from RAM, it is also stored in the cache memory based on the assumption that the same data or instruction may be needed in the near future. This phenomenon is known as temporal locality.
    • If certain data is referenced, there is a high probability that it will be referenced again in the near future, making temporal locality a key optimization factor in caching.
  • Spatial Locality:
    • Spatial locality assumes that if a memory location has been accessed, there is a high likelihood that a nearby or consecutive memory location will be accessed soon after. To capitalize on this, nearby memory references are also stored in the cache memory for faster access.
    • For instance, the traversal of a one-dimensional array in any instruction set benefits from spatial locality optimization.
    • Spatial locality enhances caching efficiency by anticipating and preloading adjacent memory locations that are likely to be accessed shortly.

Virtual Memory

Implementation of Virtual Memory

  • To implement virtual memory (VM), a designated portion of the hard disk (HDD) is allocated by the system. This allocated portion can be either a file or a separate partition.
  • In Windows, this allocated space is represented by a file named pagefile.sys, while in Linux, a distinct partition is often used for virtual memory.
  • When the system requires more memory (RAM) than is currently available, it transfers some of its data from the main memory (RAM) to the hard disk drive.
  • The additional memory doesn't physically exist in RAM; rather, it is a storage space on the disk. This implementation is achieved through a process known as swapping, involving the exchange of data between the main memory and the hard disk.
  • This swapping mechanism allows the system to create an illusion of extended memory space, efficiently managing memory demands beyond the physical limits of RAM.

Address Space and Memory Space

  • Virtual Address and Address Space:
    • An address used by a programmer is referred to as a virtual address, and the collective set of these addresses constitutes the address space.
    • The address space represents the range of virtual addresses that a program can use during its execution.
    • It provides an abstraction for the programmer, offering a seemingly continuous and expansive range of addresses, regardless of the underlying physical memory layout.
  • Physical Address and Memory Space:
    • An address in the main memory, corresponding to a location where data or instructions are stored, is termed a physical address. The set of these addresses constitutes the memory space.
    • Memory space represents the actual locations within the physical memory hardware where data is stored and can be directly accessed.
    • It reflects the real and finite capacity of the physical memory modules installed in the computer system.
  • Each address that is referenced by the CPU goes through an address mapping (or address translation) from so called virtual address to a physical address in main memory.
  • Virtual memory system provides a mechanism for transalting program-generated addresses into correct main memory locations dynamically.
  • The address translation or mapping is handled automatically by the hardware by means of a mapping table.

Memory Table for Mapping a Virtual Address

  • Virtual addresses, typically processed through memory mapping tables, are translated to physical addresses or mapped. The process can be better understood with the help of the following steps:
  • First, the virtual address is received in the virtual address register.
  • Subsequently, the virtual address is sent to the memory mapping table, which holds crucial information about the location of the address in the main memory and its accessibility.
  • The details, including the location of the address in the main memory, are stored in the memory table buffer register.
  • This information is then transferred to the main memory address register, now represented as a physical address, where it is stored.
  • With the physical address, the data in the main memory can be accessed.
  • The accessed data is stored in the main memory buffer register.

There are two primary virtual memory management techniques that handle the mapping from virtual addresses to physical addresses:

  1. Paging (Specifically Known as Demand Paging)

    Paging is a virtual memory management technique that divides both virtual and physical memory into fixed-sized pages. When a process needs data from the disk, only the necessary pages are loaded into the main memory. Demand Paging optimizes memory usage by bringing in data on-demand, reducing the initial load time and allowing for more efficient utilization of resources.

  2. Segmentation (Demand Segmentation)

    Segmentation is another virtual memory management approach that divides memory into variable-sized segments. Each segment represents a logical unit, such as a function or a data structure. When a process requires a specific segment, only that segment is loaded into memory. Demand Segmentation allows for flexibility in managing memory spaces and is particularly useful in scenarios where the size of data structures varies dynamically.

References