Basic Input/Output Interface
Programmable Peripheral Interface (8255)
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The 8085 microprocessor faced difficulties in terms of I/O interfacing capability due to limited
data and address buses. To address this issue and enhance the I/O capabilities, Intel introduced the
8255 IC, which significantly increased interfacing capacities.
Basics of 8255
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The 8255 Programmable Peripheral Interface is designed to increase the I/O interfacing
capability of microprocessors.
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It has 24 I/O pins that can be grouped into three 8-bit parallel ports: Port A, Port B, and Port
C.
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Port C can be used as individual bits or can be split into two 4-bit parts: Cupper
(C7 - C4) and Clower (C3 - C0).
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The 8255 operates in the following modes:
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I/O Modes:
- Mode 0: Basic Input/Output
- Mode 1: Strobed Input/Output
- Mode 2: Bi-Directional Bus
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BSR (Bit Set/Reset) Mode: This mode is used to set or reset individual bits in Port C.
Block Diagram
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Interfacing Requirement:
- The need for interfacing arises because of the difference in operating speeds between
the microprocessor and the peripherals. Microprocessors operate at high speeds, while
peripherals like keyboards, displays, and printers operate at comparatively lower
speeds.
- The 8255 Programmable Peripheral Interface helps manage this speed mismatch by providing
a buffer and control logic that allows the microprocessor to communicate efficiently
with the peripherals.
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Port Connections:
- Port A: This port can be configured as an 8-bit input or output port
and is connected to I/O devices that require higher data transfer rates or need to
handle 8-bit data simultaneously.
- Port B: Similar to Port A, Port B can also be configured as an 8-bit
input or output port, allowing it to interface with various I/O devices.
- Port C: This port can be split into two 4-bit ports (Cupper
and Clower). It can be used for controlling individual bits or for
interfacing with devices that require less data transfer.
- Control Port: The control port is used by the microprocessor to
configure and control the operation of Ports A, B, and C. The microprocessor uses the
read (RD), write (WR), and chip select (CS) signals to access and manage the control
port.
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Block Diagram Overview:
- Data Bus Buffer: This part of the 8255 is connected to the system data
bus. It transfers data between the microprocessor and the 8255.
- Read/Write Control Logic: This section manages the read and write
operations between the microprocessor and the 8255. It generates the appropriate control
signals based on the input from the microprocessor.
- Group A and Group B Control: The control logic is divided into two
groups, A and B, each controlling one of the ports (A or B) and a portion of Port C.
This allows for flexible configuration of the ports.
- Ports (A, B, and C): These ports are connected to the I/O devices. The
configuration of these ports is managed by the control registers.
Keyboard and Display Controller (8279)
The 8279 is a programmable keyboard and display interface designed by Intel to manage input from a
keyboard and output to a display. It helps in interfacing keyboards and displays with a microprocessor,
providing efficient data entry and display management.
Features
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The 8279 is designed by Intel.
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It supports a 64-contact key matrix along with two additional keys: "CONTROL" and "SHIFT".
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It provides three operation modes (or input modes):
- Scanned Keyboard Mode: In this mode, the keys are scanned row by row for key presses.
- Scanned Sensor Matrix Mode: This mode is used for interfacing with sensors arranged in a
matrix form.
- Strobed Input Mode: In this mode, the input is strobed and the data is latched with each
strobe signal.
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It has an inbuilt debounce key feature to eliminate key bounce issues.
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It provides a 16-byte display RAM to display up to 16 digits, allowing for efficient interfacing
and display of characters.
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It offers two output modes:
- Left Entry Mode: Data is entered from the left, similar to a typewriter.
- Right Entry Mode: Data is entered from the right, similar to a calculator.
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The interrupt output of the 8279 can be used to notify the CPU of a key press detection, which
eliminates the need for software polling. This means the CPU can perform other tasks and respond
to key presses as they occur.
8254 Programmable Interval Timer
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The 8254 is used to generate finite delays. It has three integrated counters, each with a capacity
of 16 bits.
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Why do we use the 8254?
The initial versions of Intel microprocessors, such as the 8085 and 8086, did not have an integrated
timer. Without a hardware timer, generating delays required executing software loops, which had two
main issues:
- The microprocessor would be busy while executing the delay program, meaning it couldn't
perform other tasks simultaneously.
- The accuracy of the timing would depend on the execution time of the instructions, which
could vary.
These issues are resolved by using the 8254 IC.
Features of 8254 PIT IC
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The 8254 is designed to work with various microprocessors, including the 8085 and 8086.
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The 8254 is used as a timer to generate hardware delays.
Difference between hardware delay and software delay: A hardware delay is
generated by a dedicated timer IC, allowing the microprocessor to perform other tasks during the
delay period. In contrast, a software delay requires the microprocessor to execute a delay
program, making it unavailable for other tasks during the delay.
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The 8254 can be used as a real-time clock or as a square wave generator.
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Hardware delay is more useful than software delay because the microprocessor is not actively
involved in generating the delay. When the 8254 generates a delay, the microprocessor is free to
execute other programs.
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The 8254 has three independent 16-bit down counters.
Down Counter: A down counter starts from a specified value and counts down to
zero.
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These counters can operate in BCD (Binary-Coded Decimal) or binary mode.
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Once a counter finishes counting (i.e., the required delay is reached), the 8254 interrupts the
microprocessor.
Programmable Communication Interface (8251)
Basics of 8251
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The 8251 is a programmable chip designed for synchronous and asynchronous serial data
communication.
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The 8251A is an advanced version of the 8251, with additional features and improvements.
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The control logic of the 8251 is connected with the microprocessor to determine the function of
the 8251. The control logic essentially manages the mode of operation and the configuration of
the 8251.
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The 8251 converts parallel data to serial format for transmission and converts serial data to
parallel format for reception.
Working of 8251
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Transmitter Section:
- Receives parallel data from the microprocessor.
- Converts the parallel data into serial format.
- Transmits the serial data on the TxD (Transmit Data) line.
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Receiver Section:
- Receives serial data on the RxD (Receive Data) line.
- Converts the serial data into parallel format.
- Transfers the parallel data to the microprocessor.
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Data transmission can be done for both synchronous and asynchronous data transfer.
Control Signals of 8251
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CS (Chip Select):
An active low signal that selects the 8251 for communication with the microprocessor. When this
signal is low, the 8251 is enabled for communication.
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RD (Read):
An active low signal used to read data from the 8251. When this signal is low, the
microprocessor reads data from the 8251's data bus.
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WR (Write):
An active low signal used to write data to the 8251. When this signal is low, the microprocessor
writes data to the 8251's data bus.
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C/D (Control/Data):
This signal determines whether the data being transferred is control information or actual data.
When C/D is high, the data is control information; when low, the data is actual communication
data.
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RESET:
An active high signal that resets the 8251, clearing the control registers and initializing the
device.
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CLK (Clock):
Provides the timing signal necessary for the 8251 to operate. The clock signal synchronizes the
data transmission and reception processes.
Interrupts
Interrupts are signals that inform the processor about the occurrence of an event, allowing the processor
to temporarily halt its current execution and address the event. Interrupts can be classified into two
main types: hardware interrupts and software interrupts.
Hardware Interrupts
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Definition:
Hardware interrupts are generated by external hardware devices, such as keyboards, mice,
printers, or other peripheral devices, to signal the processor that an event has occurred that
requires immediate attention.
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Characteristics:
- Triggered by external devices.
- Used for real-time processing and handling of external events.
- Examples include interrupts from a mouse click or a keystroke.
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Process:
- The external device sends an interrupt signal to the processor.
- The processor pauses its current tasks and saves the current state.
- The processor executes the interrupt service routine (ISR) to handle the event.
- After the ISR completes, the processor resumes its previous tasks.
Software Interrupts
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Definition:
Software interrupts are generated by executing specific instructions in the software, typically
used to request system services from the operating system.
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Characteristics:
- Triggered by software instructions.
- Used for system calls and to handle software events.
- Examples include system calls for file operations or memory allocation.
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Process:
- The software executes a specific interrupt instruction.
- The processor recognizes the software interrupt and pauses the current tasks.
- The processor executes the corresponding interrupt service routine (ISR) to perform the
requested service.
- After the ISR completes, the processor resumes its previous tasks.
8259 Programmable Interrupt Controller (PIC)
The 8259 Programmable Interrupt Controller (PIC) is a specialized IC designed to manage hardware
interrupts and prioritize them before sending them to the processor. It is used to enhance the interrupt
handling capabilities of microprocessors.
Basics of 8259
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Purpose:
The 8259 PIC is used to handle and prioritize multiple interrupt requests from various hardware
devices, ensuring efficient interrupt management in a system.
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Interrupt Vector:
It generates an interrupt vector address that points to the appropriate interrupt service
routine (ISR) for the processor to execute.
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Compatibility:
The 8259 is designed to work seamlessly with the 8085, 8086, and other microprocessors,
enhancing their interrupt handling capabilities.
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Interrupt Requests:
It can handle up to 8 interrupt requests (IR0-IR7), which can be expanded by cascading multiple
8259 PICs.
Features of 8259
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Priority Resolver:
The 8259 contains a priority resolver that determines the priority of the incoming interrupt
requests and services them accordingly.
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Cascading:
Multiple 8259 PICs can be cascaded to handle more than 8 interrupt requests, allowing for a
scalable interrupt management system.
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Interrupt Masking:
Individual interrupt lines can be masked using the Interrupt Mask Register (IMR), allowing
selective enabling or disabling of interrupt requests.
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Interrupt Modes:
- Fully Nested Mode: Prioritizes interrupts in a fixed order (IR0-IR7).
- Special Fully Nested Mode: Allows certain interrupts to have higher priority.
- Rotating Priority Mode: Rotates the priority of interrupts, giving each interrupt line a
chance to be the highest priority.
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End of Interrupt (EOI):
The 8259 uses an EOI command to signal the completion of an interrupt service routine, allowing
it to handle the next interrupt request.
Control Signals of 8259
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CS (Chip Select):
An active low signal that selects the 8259 for communication with the microprocessor.
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RD (Read):
An active low signal used to read data from the 8259.
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WR (Write):
An active low signal used to write data to the 8259.
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INT (Interrupt):
An active high signal sent to the processor to indicate that an interrupt request has occurred.
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INTA (Interrupt Acknowledge):
An active low signal sent by the processor to the 8259 to acknowledge the receipt of the
interrupt request.
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SP/EN (Slave Program/Enable Buffer):
Determines whether the 8259 is in master or slave mode in a cascaded configuration, and can also
be used to enable buffer.
Direct Memory Access (DMA)
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Direct Memory Access (DMA) is a method that allows data to be moved from one location to another
without the direct intervention of the Central Processing Unit (CPU). This method significantly
speeds up data transfer operations within a computer system.
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DMA provides a faster way of transferring data within the computer because it bypasses the CPU,
which can be a bottleneck in data transfer operations. By allowing peripheral devices to communicate
directly with memory, DMA improves overall system performance.
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The DMA I/O technique provides direct access to memory while the microprocessor is temporarily
disabled. This means that the CPU can continue to perform other tasks while the DMA controller
handles the data transfer, leading to more efficient use of system resources.
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The DMA controller temporarily borrows the address bus, data bus, and control bus from the
microprocessor. It transfers the data directly from external devices (like disk drives or network
cards) to a series of memory locations. This direct transfer bypasses the CPU, allowing for faster
data movement.
- The 8257 DMA controller is a crucial component in computer systems, particularly for enhancing data transfer efficiency. For instance, when you want to play a high-definition video file stored on a hard disk on your computer, the DMA controller directly accesses the system's memory and the graphics card, bypassing the CPU for data transfer operations. This means that the controller efficiently moves the video data from the hard disk to the graphics card's memory without burdening the CPU, ensuring smooth playback without interruptions or slowdowns in other tasks being performed by the CPU. DMA is essential as it offloads data transfer tasks from the CPU, allowing the CPU to focus on processing instructions and running applications, ultimately improving overall system performance and ensuring efficient handling of data-intensive tasks.
Basic DMA Operations
Two control signals are used to request and acknowledge a DMA transfer in a microprocessor-based
system. These two signals are:
- HOLD: The HOLD signal is used by the DMA controller to request control of the system
buses from the CPU.
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The HOLD signal is an input to the processor used to request DMA action. When the DMA
controller
needs to transfer data, it asserts the HOLD signal, asking the CPU to release control of
the
buses.
- HLDA (Hold Acknowledge): The HLDA signal is used by the CPU to acknowledge that it has
relinquished control of the system buses to the DMA controller.
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The HLDA (Hold Acknowledge) signal is an output from the processor that acknowledges the
DMA
action. When the CPU receives the HOLD signal, it finishes its current operation, places
the
buses in a high-impedance state (effectively disconnecting from them), and then asserts
the HLDA
signal to indicate that the DMA controller can take control of the buses.
Note: The HOLD signal has the highest priority compared to other interrupt signals like INTR
(Interrupt Request) and NMI (Non-Maskable Interrupt). However, the RESET signal has the absolute
highest priority.
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When the HLDA signal becomes active, it indicates that the processor has put its buses in a
high-impedance state. In this state, the buses are effectively disconnected from the processor,
allowing the DMA controller to take over and transfer data directly between I/O devices and
memory. This means the microprocessor is free to execute other tasks or go into a low-power
state.
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DMA operations occur directly between I/O devices and memory without involving the
microprocessor. This direct transfer method significantly speeds up data transfer processes and
frees up the CPU to perform other tasks, leading to more efficient system performance.
DMA Read and Write Operations
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DMA Read Operation:
- The DMA controller asserts the HOLD signal to request control of the system buses from
the CPU.
- The CPU finishes its current operation, places the buses in a high-impedance state, and
asserts the HLDA signal.
- The DMA controller takes control of the buses and reads data from the memory address
specified in the DMA request.
- The data is transferred from memory to the I/O device.
- Once the transfer is complete, the DMA controller deasserts the HOLD signal, and the CPU
regains control of the buses.
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DMA Write Operation:
- The DMA controller asserts the HOLD signal to request control of the system buses from
the CPU.
- The CPU finishes its current operation, places the buses in a high-impedance state, and
asserts the HLDA signal.
- The DMA controller takes control of the buses and writes data to the memory address
specified in the DMA request.
- The data is transferred from the I/O device to memory.
- Once the transfer is complete, the DMA controller deasserts the HOLD signal, and the CPU
regains control of the buses.
8237 DMA Controller
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Introduction:
The 8237 DMA controller is a programmable device used to manage DMA operations, allowing
peripheral devices to directly read from and write to memory without CPU intervention.
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Features:
- Contains four independent DMA channels, each capable of transferring data between memory
and I/O devices.
- Supports both memory-to-memory and peripheral-to-memory transfers.
- Each channel has a 64KB address range.
- Provides data transfer modes such as single transfer, block transfer, demand transfer,
and cascade mode.
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Addressing:
The 8237 DMA controller uses a base address and a current address register for each channel to
keep track of the memory locations involved in the transfer.
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Transfer Modes:
- Single Transfer Mode: Transfers a single byte of data per request.
- Block Transfer Mode: Transfers a block of data in a single burst.
- Demand Transfer Mode: Continues transferring data as long as the peripheral is
requesting it.
- Cascade Mode: Used for cascading multiple DMA controllers to handle more channels.