Basic Input/Output Interface

Basics of 8255

• The 8255 Programmable Peripheral Interface is designed to increase the I/O interfacing capability of microprocessors.
• It has 24 I/O pins that can be grouped into three 8-bit parallel ports: Port A, Port B, and Port C.
• Port C can be used as individual bits or can be split into two 4-bit parts: C_upper (C₇ - C₄) and C_lower (C₃ - C₀).
• The 8255 operates in the following modes:
  1. I/O Modes:
     • Mode 0: Basic Input/Output
     • Mode 1: Strobed Input/Output
     • Mode 2: Bi-Directional Bus
  2. BSR (Bit Set/Reset) Mode: This mode is used to set or reset individual bits in Port C.

Control Signals of 8255

• RD → Active low signal.
  When RD is active, the microprocessor reads data from the selected port of the 8255.
• WR → Active low signal.
  When WR is active, the microprocessor writes data to the selected port of the 8255.
• RESET → Active high signal.
  When RESET is active, it clears the control registers and sets all ports in input mode.
• CS, A₀, and A₁ → Chip Select and Address Lines.

   __
   CS   A1   A0
   0    0    0    Port A 
   0    0    1    Port B 
   0    1    0    Port C 
   0    1    1    Control Register 
   1    X    X    8255 not selected
                          

  The above table shows the selection of ports or the control register based on the values of CS, A₀, and A₁.

Block Diagram

• Interfacing Requirement:
  • The need for interfacing arises because of the difference in operating speeds between the microprocessor and the peripherals. Microprocessors operate at high speeds, while peripherals like keyboards, displays, and printers operate at comparatively lower speeds.
  • The 8255 Programmable Peripheral Interface helps manage this speed mismatch by providing a buffer and control logic that allows the microprocessor to communicate efficiently with the peripherals.
• Port Connections:
  • Port A: This port can be configured as an 8-bit input or output port and is connected to I/O devices that require higher data transfer rates or need to handle 8-bit data simultaneously.
  • Port B: Similar to Port A, Port B can also be configured as an 8-bit input or output port, allowing it to interface with various I/O devices.
  • Port C: This port can be split into two 4-bit ports (C_upper and C_lower). It can be used for controlling individual bits or for interfacing with devices that require less data transfer.
  • Control Port: The control port is used by the microprocessor to configure and control the operation of Ports A, B, and C. The microprocessor uses the read (RD), write (WR), and chip select (CS) signals to access and manage the control port.
• Block Diagram Overview:
  • Data Bus Buffer: This part of the 8255 is connected to the system data bus. It transfers data between the microprocessor and the 8255.
  • Read/Write Control Logic: This section manages the read and write operations between the microprocessor and the 8255. It generates the appropriate control signals based on the input from the microprocessor.
  • Group A and Group B Control: The control logic is divided into two groups, A and B, each controlling one of the ports (A or B) and a portion of Port C. This allows for flexible configuration of the ports.
  • Ports (A, B, and C): These ports are connected to the I/O devices. The configuration of these ports is managed by the control registers.

Features

• The 8279 is designed by Intel.
• It supports a 64-contact key matrix along with two additional keys: "CONTROL" and "SHIFT".
• It provides three operation modes (or input modes):
  1. Scanned Keyboard Mode: In this mode, the keys are scanned row by row for key presses.
  2. Scanned Sensor Matrix Mode: This mode is used for interfacing with sensors arranged in a matrix form.
  3. Strobed Input Mode: In this mode, the input is strobed and the data is latched with each strobe signal.
• It has an inbuilt debounce key feature to eliminate key bounce issues.
• It provides a 16-byte display RAM to display up to 16 digits, allowing for efficient interfacing and display of characters.
• It offers two output modes:
  1. Left Entry Mode: Data is entered from the left, similar to a typewriter.
  2. Right Entry Mode: Data is entered from the right, similar to a calculator.
• The interrupt output of the 8279 can be used to notify the CPU of a key press detection, which eliminates the need for software polling. This means the CPU can perform other tasks and respond to key presses as they occur.

Features of 8254 PIT IC

• The 8254 is designed to work with various microprocessors, including the 8085 and 8086.
• The 8254 is used as a timer to generate hardware delays.
  Difference between hardware delay and software delay: A hardware delay is generated by a dedicated timer IC, allowing the microprocessor to perform other tasks during the delay period. In contrast, a software delay requires the microprocessor to execute a delay program, making it unavailable for other tasks during the delay.
• The 8254 can be used as a real-time clock or as a square wave generator.
• Hardware delay is more useful than software delay because the microprocessor is not actively involved in generating the delay. When the 8254 generates a delay, the microprocessor is free to execute other programs.
• The 8254 has three independent 16-bit down counters.
  Down Counter: A down counter starts from a specified value and counts down to zero.
• These counters can operate in BCD (Binary-Coded Decimal) or binary mode.
• Once a counter finishes counting (i.e., the required delay is reached), the 8254 interrupts the microprocessor.

Basics of 8251

• The 8251 is a programmable chip designed for synchronous and asynchronous serial data communication.
• The 8251A is an advanced version of the 8251, with additional features and improvements.
• The control logic of the 8251 is connected with the microprocessor to determine the function of the 8251. The control logic essentially manages the mode of operation and the configuration of the 8251.
• The 8251 converts parallel data to serial format for transmission and converts serial data to parallel format for reception.

Working of 8251

• Transmitter Section:
  • Receives parallel data from the microprocessor.
  • Converts the parallel data into serial format.
  • Transmits the serial data on the TxD (Transmit Data) line.
• Receiver Section:
  • Receives serial data on the RxD (Receive Data) line.
  • Converts the serial data into parallel format.
  • Transfers the parallel data to the microprocessor.
• Data transmission can be done for both synchronous and asynchronous data transfer.

Control Signals of 8251

• CS (Chip Select):
  An active low signal that selects the 8251 for communication with the microprocessor. When this signal is low, the 8251 is enabled for communication.
• RD (Read):
  An active low signal used to read data from the 8251. When this signal is low, the microprocessor reads data from the 8251's data bus.
• WR (Write):
  An active low signal used to write data to the 8251. When this signal is low, the microprocessor writes data to the 8251's data bus.
• C/D (Control/Data):
  This signal determines whether the data being transferred is control information or actual data. When C/D is high, the data is control information; when low, the data is actual communication data.
• RESET:
  An active high signal that resets the 8251, clearing the control registers and initializing the device.
• CLK (Clock):
  Provides the timing signal necessary for the 8251 to operate. The clock signal synchronizes the data transmission and reception processes.

Hardware Interrupts

• Definition:
  Hardware interrupts are generated by external hardware devices, such as keyboards, mice, printers, or other peripheral devices, to signal the processor that an event has occurred that requires immediate attention.
• Characteristics:
  • Triggered by external devices.
  • Used for real-time processing and handling of external events.
  • Examples include interrupts from a mouse click or a keystroke.
• Process:
  • The external device sends an interrupt signal to the processor.
  • The processor pauses its current tasks and saves the current state.
  • The processor executes the interrupt service routine (ISR) to handle the event.
  • After the ISR completes, the processor resumes its previous tasks.

Software Interrupts

• Definition:
  Software interrupts are generated by executing specific instructions in the software, typically used to request system services from the operating system.
• Characteristics:
  • Triggered by software instructions.
  • Used for system calls and to handle software events.
  • Examples include system calls for file operations or memory allocation.
• Process:
  • The software executes a specific interrupt instruction.
  • The processor recognizes the software interrupt and pauses the current tasks.
  • The processor executes the corresponding interrupt service routine (ISR) to perform the requested service.
  • After the ISR completes, the processor resumes its previous tasks.

Basics of 8259

• Purpose:
  The 8259 PIC is used to handle and prioritize multiple interrupt requests from various hardware devices, ensuring efficient interrupt management in a system.
• Interrupt Vector:
  It generates an interrupt vector address that points to the appropriate interrupt service routine (ISR) for the processor to execute.
• Compatibility:
  The 8259 is designed to work seamlessly with the 8085, 8086, and other microprocessors, enhancing their interrupt handling capabilities.
• Interrupt Requests:
  It can handle up to 8 interrupt requests (IR0-IR7), which can be expanded by cascading multiple 8259 PICs.

Features of 8259

• Priority Resolver:
  The 8259 contains a priority resolver that determines the priority of the incoming interrupt requests and services them accordingly.
• Cascading:
  Multiple 8259 PICs can be cascaded to handle more than 8 interrupt requests, allowing for a scalable interrupt management system.
• Interrupt Masking:
  Individual interrupt lines can be masked using the Interrupt Mask Register (IMR), allowing selective enabling or disabling of interrupt requests.
• Interrupt Modes:
  • Fully Nested Mode: Prioritizes interrupts in a fixed order (IR0-IR7).
  • Special Fully Nested Mode: Allows certain interrupts to have higher priority.
  • Rotating Priority Mode: Rotates the priority of interrupts, giving each interrupt line a chance to be the highest priority.
• End of Interrupt (EOI):
  The 8259 uses an EOI command to signal the completion of an interrupt service routine, allowing it to handle the next interrupt request.

Control Signals of 8259

• CS (Chip Select):
  An active low signal that selects the 8259 for communication with the microprocessor.
• RD (Read):
  An active low signal used to read data from the 8259.
• WR (Write):
  An active low signal used to write data to the 8259.
• INT (Interrupt):
  An active high signal sent to the processor to indicate that an interrupt request has occurred.
• INTA (Interrupt Acknowledge):
  An active low signal sent by the processor to the 8259 to acknowledge the receipt of the interrupt request.
• SP/EN (Slave Program/Enable Buffer):
  Determines whether the 8259 is in master or slave mode in a cascaded configuration, and can also be used to enable buffer.

Basic DMA Operations

Two control signals are used to request and acknowledge a DMA transfer in a microprocessor-based system. These two signals are:

1. HOLD: The HOLD signal is used by the DMA controller to request control of the system buses from the CPU.
   • The HOLD signal is an input to the processor used to request DMA action. When the DMA controller needs to transfer data, it asserts the HOLD signal, asking the CPU to release control of the buses.
2. HLDA (Hold Acknowledge): The HLDA signal is used by the CPU to acknowledge that it has relinquished control of the system buses to the DMA controller.
   • The HLDA (Hold Acknowledge) signal is an output from the processor that acknowledges the DMA action. When the CPU receives the HOLD signal, it finishes its current operation, places the buses in a high-impedance state (effectively disconnecting from them), and then asserts the HLDA signal to indicate that the DMA controller can take control of the buses.

Note: The HOLD signal has the highest priority compared to other interrupt signals like INTR (Interrupt Request) and NMI (Non-Maskable Interrupt). However, the RESET signal has the absolute highest priority.

• When the HLDA signal becomes active, it indicates that the processor has put its buses in a high-impedance state. In this state, the buses are effectively disconnected from the processor, allowing the DMA controller to take over and transfer data directly between I/O devices and memory. This means the microprocessor is free to execute other tasks or go into a low-power state.
• DMA operations occur directly between I/O devices and memory without involving the microprocessor. This direct transfer method significantly speeds up data transfer processes and frees up the CPU to perform other tasks, leading to more efficient system performance.

DMA Read and Write Operations

• DMA Read Operation:
  1. The DMA controller asserts the HOLD signal to request control of the system buses from the CPU.
  2. The CPU finishes its current operation, places the buses in a high-impedance state, and asserts the HLDA signal.
  3. The DMA controller takes control of the buses and reads data from the memory address specified in the DMA request.
  4. The data is transferred from memory to the I/O device.
  5. Once the transfer is complete, the DMA controller deasserts the HOLD signal, and the CPU regains control of the buses.
• DMA Write Operation:
  1. The DMA controller asserts the HOLD signal to request control of the system buses from the CPU.
  2. The CPU finishes its current operation, places the buses in a high-impedance state, and asserts the HLDA signal.
  3. The DMA controller takes control of the buses and writes data to the memory address specified in the DMA request.
  4. The data is transferred from the I/O device to memory.
  5. Once the transfer is complete, the DMA controller deasserts the HOLD signal, and the CPU regains control of the buses.