Key concepts of Computer Organization and Architecture

Internal hardware organization of a digital computer

• Internal hardware organization of a digital computer can be orgaized in 3 format.

1. Set of register it contains and their function.
   • How many general purpose register are there.
   • Size of instruction register.
2. Sequence of microoperations performed on binary information stored in registers.
3. Control signals that initiate the sequence of microoperations that we want to perform.
   • Suppose if we want to add two numbers (A + B), they will not be directly added, there must be some control function will be used which will be contolling the value of A and B, and which will also control this operation to happen.

What is RTL?

• The symbolic notation used to describe the microoperation transfers among registers is called Register Transfer Language.
• It is basically a language and we know that a language have its own syntax and rules and RTL is used while we are working with computer organization and its design.

Key points for RTL

• A symbolic language.
• A convenient tool for describing the internal organization of digital computers in consice/precise manner.
• Can also be used to facilitate the design process of digital systems.

Rules of RTL

• Registers are designated by capital letters, some time followed by numbers (e.g. A, R1, IR)
• Often the name indicate function:
  • MAR : Memory Address Regsiter
  • PC : Program Counter
  • IR : Instruction Register

Address registers

• We know CPU reads and write data on memory. So this address register is used to store memory address of data for CPU.
• It picks data from memory like addresses, addresses stored in address register, AR gives the address to memory, memory then decodes the addresses and then fetches the data from RAM.
• Size = 12 bits.

Memory Data Register

• The Memory Data Register (MDR) is a component of a computer's CPU that temporarily holds data fetched from the computer's memory. When the CPU reads data from memory, it's stored in the MDR before being processed. Similarly, when the CPU writes data to memory, it places the data in the MDR before sending it to the memory. The MDR essentially acts as a temporary storage location for data during memory read and write operations.

Memory Buffer Register (MBR)

• The Memory Buffer Register (MBR) is used in input/output (I/O) operations in computer systems. It holds data that is being transferred between the CPU and an I/O device, such as a hard drive or network interface. The MBR helps in coordinating data transfers between the CPU and I/O devices, ensuring efficient communication and minimizing bottlenecks. It serves as a temporary buffer to hold data that is moving between the CPU and external devices.

Accumulator

• It stores intermediate results from the ALU and temporary information of operands.
• It is also called a Processor Register.
• The accumulator register retrieves data from memory and temporarily stores it before transferring it to the ALU. This intermediate step allows data to be efficiently accessed by the ALU for various arithmetic and logical operations. By doing so, the processor optimizes performance by minimizing direct memory access during calculations.

Instruction Register

• Stores instructions that need to be executed.

Instructions basically consist of three parts:

1. I → It is the MSB
   • Could be 0 or 1.
   • If I = 0, it means direct addressing.
   • If I = 1, it indicates indirect addressing.
   • If the value is 0, then it directly goes to that location to fetch data and gives it to the accumulator.
   • If the value is 1, it indicates indirect addressing. In this case, the system follows a sequence where it moves to the 1st location, which then directs it to the 2nd location, and from there, to the 3rd location where the data is located.
2. Op code → The operation to be performed, like addition, subtraction, multiplication, or division.
3. Operands → Data on which the operation has to be performed.
   • The operand part has the address of the data on which we have to perform the operation.

• The Instruction Register is typically 16 bits long, with 12 bits for operands, 3 bits for the OP code, and 1 bit for I.

Program Counter

• Definition: The Program Counter (PC) register is a special-purpose processor register that holds the memory address of the next instruction to be fetched and executed.

Control functions

• Often actions need to only occur if a certain condition is true.
• This is similar to an "if" statement in a programming language. In digital systems this is often done via control signal called a control function.
• If the signal is 1, then the action takes place.
• This is represented as:
  P: R2 ← R1
  Which means "If p = 1, then load the content of register R1 into register R2" i.e. if (P = 1) the (R2 ← R1)

Basic Symbols used for Register Transfer

Examples:

• If(P = 1) then (R2 ← R1)
  Symbol - P : R2 ← R1
• Q⇒ The data of register R5 & R9 is transfered to R3 & R10 respectively only when T = 1
  A⇒ T : R3 ← R5, R10 ← R9
• Q⇒ The content of register R1 & R6 are added & result is transfered into register MDR only when P + Q = 1
  A⇒ P + Q : MDR ← R1 + R6
• Q⇒ The difference of two register R2 & R4 is to be stored in register IR when either P or Q is 1
  A⇒ P ⊕ Q : IR ← (R2 - R4)

Hardware implementation of controlled transfers

1- Content of register R1 and R6 are added & result is transfered into register MDR only when P + Q = 1. ↓

2- The difference of two register R2 and R4 is to be stored in register IR wen either P or Q is 1. ↓

Bus Transfer

• In a digital system of registers, a path must be provided to move information.
• A bus is made up of a collection of common lines, one for each bit of a register, that are used to transfer binary data.
• There are two methods in bus transfer:
  • Bus transfer using Multiplexer
  • Bus transfer using Three states bus buffer

Bus transfer using multiplexer

• Multiplexer selects the source register whose binary information is kept on the bus.
• Key terms to understand before desinging a bus system using multiplexer.
• There would always be a scenerio given.
• Example question scenerio : Construct a bus system of 8 register with 16 bits.

• Now according to the scenerio.
  1. How many multiplexer are required.
  2. What would be the size of each multiplexer.
  3. How many selection lines?

• In the above scenerio of 8 registers with 16 bits
  • Number of multiplexer = 16
  • Size of each multiplexer = k x 1 = 8 x 1
  • And we know that for 8 x 1 multiplexer there are 3 selection lines.

Construct a bus system for 4 register and each bit = 4

Construct a bus system for eight 4 bit register

Design a bus system for four 8 bit register

Bus System Using Three-State Buffer

• A three-state gate is a digital circuit that exhibits three states, two of which are signals equivalent to logic 0 and 1, similar to a conventional gate. The third state is the high-impedance state, which restricts the flow of input towards the output.
• The high-impedance state behaves like an open circuit, which means that the output is disconnected and does not have logical significance.
• A three-state bus buffer has a control input that determines the output state. When the control input is equal to 1, the output is enabled, and the gate behaves like a conventional buffer with the output equal to the normal input. When the control input is 0, the output is disabled, and the data goes into the high-impedance state, regardless of the value of the normal input.

• Normally, in a buffer, the input delivered equals the output generated. However, in a three-state buffer, the second input is the control input.
• When C = 1, only in that case, A will be transferred as the circuit is closed. If C = 0, the state is high-impedance as it is an open circuit.

Arithmetic Microoperations

• The basic arithmetic operations include addition, subtraction, complement, increment, and decrement.
• Some symbolic representations of arithmetic microoperations are ↓ (down arrow).

• Multiplication and division are valid operations, but they are not considered basic microoperations.

Logic Microoperations

• Logic micro-operations consider each bit of the register separately and treat them as binary variables.
• Example ↓

Selective Set: The selective-set operation sets bits to 1 in register A where there are corresponding 1s in register B.

• The two leftmost bits of B are 1's, so the corresponding bits of A are set to 1. The OR micro-operation can be used to selectively set bits of a register.

Selective Complement: The selective-complement operation complements bits in A where there are corresponding 1s in B. It does not affect bit positions that have 0s in B. For example:

• Again, the two leftmost bits of B are 1s, so the corresponding bits of A are complemented. The exclusive-OR micro-operation can be used to selectively complement.

Selective Clear: The selective clear operation clears to 0 the bits in A only where there are corresponding 1s in B. For example ↓

• Again, the two leftmost bits of B are 1s, so the corresponding bits of A are cleared to 0.

Mask Operation: The mask operation is similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0s in B. The mask operation is an AND micro-operation as seen from the following numerical example:

• The two rightmost bits of A are cleared because the corresponding bits of B are 0s. The two leftmost bits are left unchanged because the corresponding bits of B are 1s.

Insertion Operation: The insert operation inserts a new value into a group of bits. This is done by first masking the bits and then ORing them with the required value. For example, suppose that an A register contains eight bits, 0110 1010. To replace the four leftmost bits by the value 1001, we first mask the four unwanted bits:

• The mask operation is an AND micro-operation, and the insert operation is an OR micro-operation.

Clear Operation: The clear operation compares the words in A and B and produces an all-0's result if the two numbers are equal. This operation is achieved by an exclusive-OR micro-operation, as shown by the following example:

• When A and B are equal, the two corresponding bits are either both 0 or both 1. In either case, the exclusive-OR operation produces a 0. The all-0's result is then checked to determine if the two numbers were equal.

Shift Micro-Operations

• Shift micro-operations are used for the serial transfer of data. The contents of a register can be shifted to the left or the right. There are three types of shifts: logical, circular, and arithmetic.
• A logical shift is one that transfers 0 through the serial input. The symbols shl and shr are used to show logical shift-left and shift-right micro-operations. For example ↓

• The circular shift (also known as a rotate operation) circulates the bits of the register around the two ends without loss of information. This is accomplished by connecting the serial output of the shift register to its serial input. We will use the symbols cil and cir for the circular shift left and right, respectively.

• An arithmetic shift shifts a signed binary number to the left or right. An arithmetic shift-left multiplies a signed binary number by 2. An arithmetic shift-right divides the number by 2. Arithmetic shifts must leave the sign bit unchanged because the sign of the number remains the same when it is multiplied or divided by 2.
  • The arithmetic shift-right leaves the sign bit unchanged and shifts the number to the right. Thus, Rn-1 remains the same, Rn-2 receives the bit from Rn-1. The bit in R0 is lost. The arithmetic shift-left inserts a 0 into R0 and shifts all other bits to the left. The initial bit of Rn-1 is lost and replaced by the bit from Rn-2.

• The symbolic notation for the shift micro-operations is shown in the table below:

Basic FUNDA

• Video lecture ↗

• First we should know the basic modules out of which our computer is made out of ↓

• Processor → It is a module where all instructions of program are executed.
  • Here all calculation occurs.
• Memory → Module where data is stored.
• I/O → Module by which data is brought into the machine and result is given out.

Using these basic 3 modules a computer is build.

• We have learned about the operations that are performed by ALU (Arithmetic Logical Unit) module of processor like shift operation, arithmetic, logic, etc.
• ALU basically perform operation when data and instructions (add, sub) are given to it and then it generates result.
• The ALU by itself can't finish the job, as it needs the right instructions for calculating results in a specific time. This is why another part inside the processor, called the control unit, is necessary. The control unit makes sure the timing and control signals are all set.

Why CU is important?

• The Control Unit (CU) plays a vital role in the computer's operation.
• When data arrives for processing, it can't directly enter the Arithmetic Logic Unit (ALU) as the ALU doesn't have the ability to understand what to do with the data without instructions.
• This is how it functions: Initially, the data is stored in registers, which act as temporary holding areas. Following that, the Control Unit (CU) becomes active.
• The Control Unit generates instructions that guide the ALU's actions:
• Retrieving data from the registers
• Activating specific circuits within the ALU for precise time intervals, facilitating calculations
• Providing the final calculated result once the computations are finished.
• Basically CU is that module of a processor which controls all the operations happening inside the processor.

Exploring the core components of a computer highlights a vital fact: INSTRUCTIONS are the backbone of its functioning. Without instructions, the Arithmetic Logic Unit (ALU) is directionless, unable to perform tasks.

Instruction format

• This format is stored inside memory, these are brought to processor from memory.
• This format provides a consistent way for the processor to understand and execute a wide range of instructions.

Types of instructions format

• Video lecture ⇗

• Memory Reference Instructions: These instructions involve operations that require data to be fetched from or stored into memory. They often include fields specifying memory addresses or offsets to locate the desired data. Memory reference instructions are essential for tasks like loading data into registers, storing results back to memory, and data manipulation.
• Register Reference Instructions: In these instructions, the operations are performed directly using data stored within the CPU's registers. These instructions typically include fields indicating the registers involved and the operation to be executed. Register reference instructions are commonly used for arithmetic, logic, and data manipulation tasks.
• Input/Output (I/O) Reference Instructions: I/O reference instructions manage communication between the computer and external devices. These instructions facilitate input (receiving data from external sources) and output (sending data to external devices) operations. They often include fields specifying the device or port to interact with and the data to be transferred.

Three-Address Instruction

Consider the expression: X = (A + B) * (C + D)

We can represent this expression using three-address instructions, which means each instruction contains three addresses, which can be either registers or memory addresses.

                    
ADD R1, A, B      ; R1 <- M[A] + M[B]
ADD R2, C, D      ; R2 <- M[C] + M[D]
MUL X, R1, R2     ; M[X] <- R1 * R2
                    
                

Two-Address Instruction

Now, let's represent the same computation using two-address instructions:

                    
MOV R1, A        ; R1 <- M[A]
ADD R1, B        ; R1 <- R1 + M[B]
MOV R2, C        ; R2 <- M[C]
ADD R2, D        ; R2 <- R2 + M[D]
MUL R1, R2       ; R1 <- R1 * R2 
MOV X, R1        ; M[X] <- R1
                    
                

One-Address Instruction

In the one-address instruction format, we use instructions like "LOAD" (load a memory word into the accumulator) and "STORE" (store the accumulator into memory):

                    
LOAD A          ; AC <- M[A]
ADD B           ; AC <- AC + M[B]
STORE T         ; M[T] <- AC 
LOAD C          ; AC <- M[C]
ADD D           ; AC <- AC + M[D]
MUL T           ; AC <- AC * M[T]
STORE X         ; M[X] <- AC
                    
                

Zero-Address Instruction

In zero-address instructions, we utilize a stack for computation. This type of instruction set includes operations like "PUSH" and "POP" for stack manipulation, as well as arithmetic operations such as addition, subtraction, and multiplication. To represent the given expression using zero-address instructions, we need to convert the expression into postfix notation.

Here are some rules for postfix notation:

• If it's an operand, push it onto the stack.
• If it's an operator, pop the last two operands from the stack, perform the operation, and push the result back onto the stack.
• Postfix notation eliminates the need for parentheses because the order of operations is unambiguous. Operators are always applied to the last two operands on the stack.
• When evaluating postfix expressions, operators are processed from left to right.
• The stack is used to hold both operands and intermediate results during the computation.

                    
Postfix Expression: AB+CD+*

PUSH A          ; Push operand A onto the stack
PUSH B          ; Push operand B onto the stack
ADD             ; Pop the last two operands (A and B), add them, and push the result onto the stack
PUSH C          ; Push operand C onto the stack
PUSH D          ; Push operand D onto the stack
ADD             ; Pop the last two operands (C and D), add them, and push the result onto the stack
MUL             ; Pop the last two operands (result of C+D and result of A+B), multiply them, and push the result onto the stack
POP X           ; Pop the final result from the stack and store it in memory location X
                    
                

Phase 1 - Fetch

• We will see the register transfer state for fetch.
• During T₀ AR ← PC. Initially PC contains address of next instruction to be executed, that address will loaded into Address Register during first clock pulse.
  During T₁ IR ← M[AR], PC ← PC + 1. Here we have to read instruction from the memory and that instruction should be loaded into instruction register (IR stores the instruction), now for the next instruction to be executed we have to increment the PC.

Phase 2 - Decode

• T₂ AR ← IR[0-11], D₇ D₆ ... D₀ IR[12, 14], I ← IR[15].
  • I is the direct or indirect address bit.

FLow chart

AND

• It performs the AND logic operation between AC and the data stored at address given by AR. The result transferred into AC. The microoperations that execute this instruction are:
  DR ← M[AR]
  AC ← AC ∧ DR

ADD to AC

• It performs the addition of AC and the data which is stored at address given by AR. The sum is transferred into AC and the output carry C_out is transferred to the E flip-flop. The microoperations needed to execute this instruction are:
  DR ← M[AR]
  AC ← AC + DR, E ← C_out

LDA: Load to AC

• This instruction transfers the data which is stored at address given by AR into AC. The microoperations needed to execute this instruction are:
  DR ← M[AR]
  AC ← DR

STA: Store AC

• This instruction stores the content of AC at the address given by AR. We can execute this instruction with one microoperation:
  M[AR] ← AC

BUN: Branch Unconditionally

• It is used when a program has a branch instruction. In this control of a program goes to the address given by AR (without checking any condition) and execute the instructions.
  PC ← AR

BSA: Branch and Save Return Address

• It is also used when a program has a branch instruction but when it moves to another program, it stores the address of current instruction. When it come back, it starts from the stored address.
  M[AR] ← PC, PC ← AR + 1

ISZ: Increment and Skip if Zero

• This instruction increments the word stored in AR, and if the incremented value is equal to 0, PC is incremented by 1.

I/O configuration

• The terminal sends and receives serial information. Each quantity of information has eight bits of an alphanumeric code.
• The serial information for the input device is shifted into the input register INPR.
• The serial information for the output device is stored in the output register OUTR.
• There two register communitcate with a communication interface serially and with the AC in parallel.

• INPR → Input Register - consists eight bits and holds an alphanumeric I/P information.
• FGI → 1-bit I/P flag is a control flip-flop.
  • 1 when new information is available in the I/P device.
  • 0 when the information is accepted by the computer.
• Initially FGI is cleared to 0.
• WHen a key is struct in the keyboard, an 8-bit alphanumeric code is shifted into INPR and the input flag FGI is set to 1.
• As long as the flag is set, the information in INPR cannot be changed by striking another key.
• The computer checks the flag bit, if it is 1, the information from INPR is tranferred in parallel into AC and FGI is cleared to 0.
• Once the flag is cleared, new information can be shifted into INPR by striking another key.

• OUTR → Output Register - consists eight bits.
• FGO → 1-bit o/p flag is a control flip-flop.
  • 0 do not load new thing.
  • 1 information from AC is transferred in parallel to OUTR.
• Initially FGO = 1, information from AC is transferred in parallel to OUTR and FGO is cleared to 0.
• O/p device accepts the coded information, prints the corresponding character and when the operation is completed, it set FGO = 1.
• The computer does not load a new character into OUTR when FGO = 0, it indicates the output device is busy.

Interrupts

• Video lecture ⇗

• Definition → It is a mechanism by which modules like I/O or memory may interrupt the normal processing of CPU.
• Interrupt is required to improve the processing efficiency of CPU.
• How does it happen?
  • CPUs are designed to execute instructions at a very high speed, often measured in gigahertz (GHz), which means they can perform a large number of operations per second. On the other hand, many external devices, such as keyboards, hard drives, or network interfaces, operate at significantly slower speeds. For instance, hard drives might transfer data at rates of megabytes per second, which is much slower compared to the billions of instructions the CPU can execute in the same amount of time.
  • Without Interrupts: Imagine a scenario where the CPU is executing a program and needs to read data from a slow external device. If interrupts were not used, the CPU would need to continuously poll (check) the external device to see if it has data ready for processing. This polling would involve the CPU repeatedly asking the device, "Are you ready yet?" and waiting for a response.
  • Wasted CPU Time: During this waiting period, the CPU would not be doing anything productive. It would spend a significant portion of its time repeatedly checking the device's status instead of executing useful instructions from the program it's supposed to run. This results in a wastage of CPU processing power and efficiency.
  • Interrupt Solution: Here's where interrupts come into play. When an external device has data ready for processing or an event occurs that requires CPU attention, the device sends an interrupt signal to the CPU. The CPU then temporarily suspends its current activities, saves its current state, and switches to the appropriate interrupt handler routine to deal with the event. This allows the CPU to efficiently manage its time. It doesn't need to constantly poll devices. Instead, it can continue executing other tasks or programs until an interrupt occurs. When an interrupt happens, the CPU switches to handling that interrupt, processes the required data or event, and then resumes its previous activities.
• In essence, interrupts allow the CPU to be more productive by not wasting time waiting for slower devices. Instead, it can work on multiple tasks in parallel, efficiently responding to external events and data availability as needed.

Interrupt Request & Interrupt Handler

• Video Lecture ⇗

• CPU is executing some task.
• User uses the keyboard to issue a high-priority command.
• This issues an interrupt request to the CPU.
• CPU suspends the current execution of the task.
• CPU executes the code written to handle / implement this command.
• CPU resumes its previous execution.
• Advantage → Efficiency of CPU improves.
• Disadvantage → Overhead required to serice the interrupt request.

Types of interrupts

1. Program interrupt:
   • It occurs when some instruction within the program creates a condition that leads to an interrupt.
   • Eg → divide by 0, arithmetic overflow (memory size is 8 bits but after addition 9 bits memory size is required.).
2. Timer interrupt:
   • It is generated by the timer present with in the processor.
   • OS sets the time to perform certain operation on regular basis.
3. Input-output interrupt:
   • Generated by I/O devices.
   • Signal successful task completion or error.
4. Hardware interrupt:
   • cause → failures related to hardware.

How to handle single interrupt?

• Video lecture ⇗

• Add interrupt cycle to instruction cycle.
• If interrupt occurs:
  1. Suspend the execution of program
  2. Saving the context i.e. current contents of PC, register values, stack contents.
  3. Determine the interrupt handler.
  4. Set PC to the starting address of the handler.
  5. Fetch & execute the instruction handler completion, resume processing of the interrpted code.
• If no interrupt
  • CPU proceeds to fetch - execute cycle.

How to handle multiple interrupts

• Video lecture ⇗

Method 1 : Disable multiple interrupts

• is a technique used in interrupt handling to temporarily prevent the CPU from responding to additional interrupts while it is already processing an interrupt. This approach ensures that the CPU completes the current interrupt handling routine without being interrupted by other interrupt requests. Once the current interrupt is fully handled, the CPU re-enables interrupts, allowing it to respond to new interrupt requests.
• Here sequential execution of interrupt occurs ↓

• Advantages :
  • Predictable Handling: Disabling multiple interrupts ensures that the CPU completes the current interrupt handling routine without being interrupted by other interrupts. This can lead to more predictable and deterministic behavior in critical tasks.
  • Simplicity: This approach can simplify the interrupt handling process, making it easier to manage and debug interrupt-related code.
  • Avoids Race Conditions: By preventing multiple interrupts from occurring simultaneously, the CPU avoids potential race conditions where multiple interrupts might interact in unexpected ways.
• Disadvantages :
  • Interrupt Latency: While the CPU is handling an interrupt with interrupts disabled, it cannot respond to other interrupts, potentially causing a delay in handling time-sensitive events.
  • Unresponsiveness: If an interrupt with high priority occurs while interrupts are disabled, the system might not be able to promptly respond, leading to reduced system responsiveness.
  • Interrupt Priority: Disabling multiple interrupts can prevent lower-priority interrupts from being serviced during the execution of a higher-priority interrupt, potentially affecting the overall system performance.

Method 2 : Give priority to interrupt

• The "give priority to interrupt" technique is an interrupt handling strategy in computer systems where different interrupts are assigned different priority levels. When multiple interrupts occur simultaneously or in quick succession, the system responds to the interrupt with the highest priority first. This approach ensures that critical or time-sensitive events are addressed promptly, even if other interrupts are pending.